Three low-level systems projects from Advanced Computer Organization at Georgia Tech — simulating a multi-level cache hierarchy, an out-of-order processor using Tomasulo's algorithm, and cache coherency protocols across multi-core processors.
These three projects were built for CS Advanced Computer Organization at Georgia Tech — one of the most technically demanding systems courses in the program. Each project required implementing a core component of modern processor architecture entirely in C, with no starter framework beyond the problem specification.
The progression moves from single-core memory hierarchy simulation through out-of-order execution to multi-core cache coherency — covering the same architectural concepts found in real processor designs at Intel, AMD, and ARM. The projects are simulation-focused: given a trace of memory accesses or instructions, the simulator must produce exact outputs matching the behavior of the hardware being modelled.
Built a configurable multi-level cache simulator in C that models the behaviour of a real processor's memory hierarchy. Given a trace of memory access addresses, the simulator processes each access through configurable L1, L2, and L3 cache levels, tracking hits, misses, and evictions at each level with exact fidelity to the hardware's behaviour.
The simulator supports multiple cache replacement protocols, selectable at runtime — making it possible to study how replacement policy affects hit rate across different access patterns and workloads.
Multi-Level Cache Hierarchy Simulated a full L1/L2/L3 cache hierarchy with configurable size, associativity, and block size at each level. On a miss at one level, the access propagates to the next — accurately modelling inclusion/exclusion policies and write-back vs write-through behaviour.
Multiple Replacement Protocols Implemented LRU (Least Recently Used), LFU (Least Frequently Used), and FIFO (First In First Out) replacement policies, each producing different eviction decisions when a cache set is full. The comparison between policies across different access traces reveals the real-world tradeoffs between implementation complexity and hit rate.
Trace-Driven Simulation The simulator reads memory access traces and produces detailed statistics: hit/miss counts per cache level, total accesses, eviction counts, and overall hit rate — allowing exact verification against known hardware behaviour.
Implemented a simulation of an out-of-order processor using Tomasulo's algorithm — the technique used in virtually every modern high-performance processor (Intel Core, AMD Ryzen, Apple Silicon) to execute instructions out of program order while maintaining correct results.
Out-of-order execution is one of the most complex techniques in processor design: instructions must be tracked through issue, execution, and writeback while resolving data hazards dynamically at runtime. The simulation models this entire pipeline cycle-accurately, paired with a branch predictor to handle control flow.
Tomasulo's Algorithm Implemented the full Tomasulo reservation station scheme — instructions are issued to reservation stations, which wait for their source operands to become available via the Common Data Bus before dispatching to execution units. This eliminates false data hazards and allows independent instructions to execute in parallel without stalling the pipeline.
Register Renaming & Data Hazard Resolution Implemented register renaming to eliminate WAR (write-after-read) and WAW (write-after-write) hazards — a critical component of out-of-order execution that lets the processor maintain a much larger effective register file than the architectural register count.
Branch Prediction Integrated a branch predictor to speculatively execute past branch instructions rather than stalling. Mispredicted branches trigger a pipeline flush and restart from the correct path — the simulator tracks prediction accuracy and its impact on overall IPC (instructions per cycle).
Cycle-Accurate Simulation The processor simulation advances cycle by cycle, modelling instruction fetch, issue, execute, and writeback with exact timing — producing IPC metrics that can be compared directly against theoretical hardware performance.
Simulated cache coherency protocols across a multi-core processor system — the mechanism that keeps each core's private cache consistent with the other cores when multiple processors share memory. This is the fundamental problem that makes multi-core processor design hard: without coherency, two cores can hold contradictory values for the same memory address.
The simulator implements and compares three progressively more sophisticated coherency protocols, each adding new cache line states to reduce unnecessary bus traffic and improve performance.
4-state protocol: Modified, Owned, Shared, Invalid. The Owned state allows a cache to supply data to other caches directly without writing back to memory first — reducing main memory traffic.
4-state protocol: Modified, Exclusive, Shared, Invalid. The Exclusive state allows a cache line to be promoted to Modified without a bus transaction if no other cache holds it — the standard protocol used in most modern processors.
6-state protocol combining both optimizations: Modified, Owned, Exclusive, Shared, Invalid, Forward. The Forward state designates one cache as the designated responder for a shared line, reducing bus contention in highly shared scenarios.
Snooping Bus Simulation Implemented a snooping-based coherency bus where each core's cache controller monitors all bus transactions. When a core reads or writes a shared address, all other caches snoop the bus and update their state accordingly — the foundation of coherency in shared-bus multi-core systems.
State Machine per Cache Line Each cache line runs a finite state machine that transitions between protocol states based on local processor requests and snooped bus transactions. Implementing all three protocols required correctly encoding the full state transition table for each — including edge cases like simultaneous requests from multiple cores.
Protocol Comparison The simulator outputs bus transaction counts, invalidation counts, and cache-to-cache transfer rates for each protocol — making it possible to quantitatively compare how the additional states in MESI and MOESIF reduce bus traffic compared to the simpler MOSI baseline.